This paper introduces an ultra-low power 1.7-2.7-GHz fractional-N sub-sampling digital PLL (SS-DPLL) for Internet-of-Things (IoT) applications targeting compliance with Bluetooth Low Energy (BLE) and IEEE802.15.4 standards. A snapshot time-to-digital converter (TDC) acts as a digital sub-sampler featuring an increased out-of-range gain and without any assistance from the traditional counting of DCO edges, thus further reducing power consumption. With a proposed DCO-divider phase rotation in the feedback path, the impact of the digital-to-time converter's (DTC's) non-linearity on the PLL is reduced and improves fractional spurs by at least 8 dB across BLE channels. Moreover, a “variable-preconditioned LMS” calibration algorithm is introduced to dynamically correct the DTC gain error with fractional frequency control word (FCW) down to 1/16384. Fabricated in 40 nm CMOS, the SS-DPLL achieves phase noise performance of -109 dBc/Hz at 1 MHz offset, while consuming a record-low power of 1.19 mW. ... Read more

This paper presents a digital active electrode (DAE) system for multi-parameter biopotential signal acquisition in portable and wearable devices. It is built around an IC that performs analog signal processing and digitization with the help
of on-chip instrumentation amplifiers, a 12 bit ADC and a digital interface. Via a standard bus, up to 16 digital active electrodes (15-channels) can be connected to a commercially available microcontroller, thus significantly reducing system
complexity and cost. In addition, the DAE utilizes an innovative functionally DC-coupled amplifier to preserve input DC signal, while still achieving state-of-the-art performance: 60 nV/sqrt(Hz) input-referred noise and 350 mV electrode-offset tolerance. A common-mode feedforward scheme improves the CMRR of an
AE pair from 40 dB to maximum 102 dB. ... Read more