This paper presents the prototype of a single channel 8-bit 0.7-GS/s A/D converter implemented in a 65-nm CMOS process. The required thresholds are generated from the resistive interpolation embedded within the preamplifier preceding the latches. The active area of the chip is 150 × 220 μm² and the total power consumption is 5.96 mW. At Nyquist, the ADC achieves 6.62 ENOB, resulting in a figure of merit equal to 86.7 fJ/conversion-step.

Ultra high-speed comparators for data-converters operating with conversion rate of 10+ GS/s are discussed. It is shown that the use of nanometer technologies and specific architectures allow comparator speeds in the 30 ps range or below. State-of-the-art schemes of latch are critically analysed and strategies for enhancing the speed are discussed. A novel scheme, the latch with embedded preamp, increases the speed of the fast scheme by almost a factor 2.