Conventional neural network hardware faces dual challenges: the diminishing returns of Moore’s Law and the intensifying constraints of the memory wall. In contrast, an emerging specialized hardware architecture, namely compute-in-memory (CIM), is gaining attention, inherently mitigating the above challenges imposed by its in-memory computing capability. However, unlike the conventional computing hardware ecosystem, which benefits from mature toolchains and well-established methodologies, current CIM architectures still lack robust infrastructure for exploring optimization opportunities and pinpointing performance bottlenecks. To address this, this thesis proposes a two-tier static profiling framework that designs and combines a Multi-Level Intermediate Representation (MLIR) profiler with a hardware-oriented profiler to identify instruction scale, memory pressure, and parallelism ceilings with low compilation overhead. It also introduces a weight-based convolutional adaptation method that effectively addresses non-sequential access issues in convolutional compilation, reducing latency and energy consumption at the cost of additional hardware overhead. Comparative experiments demonstrate that the optimized framework outperforms state-of-the-art conventional hardware in terms of latency and energy consumption for small convolutional neural network models. This result presents an exploratory path for compilation optimization on CIM architectures.