Wearable ultrasound devices for imaging and therapeutic applications demand low-power and low-area integrated circuits to interface with ultrasound transducers. In the case of ultrasound imaging front-ends, discrete time-gain compensation (TGC) simplifies gain control in ultrasound imaging (USI) ASICs, but higher gain-step resolution increases area and power dissipation, while high PSRR is needed to suppress switching noise from co-integrated HV digital circuits. This work presents a programmable-gain floating inverter low-noise amplifier (FIALNA) architecture in 28nm CMOS for low-power, wide-bandwidth USI. A thermometer-encoded variable reservoir capacitance enables fine TGC with five PVT-robust gain steps, achieving 53.6dB PSRR and an area of 0.0023mm2, an order of magnitude smaller than current PGA designs. The FIALNA dissipates 116μW and achieves 59μVrms input-referred noise, making it suitable for low-power wearable ultrasound devices.