11 records found
1
Trade-offs in buffer planning
Throughput driven unidirectional bus design for NoC applications
Buffer planning for global wires under statistical process variations
Analytic model for area-constrained optimal repeater insertion
Simultaneous analytic area and power optimization for repeater insertion
Analytic model for area and power constrained optimal repeater insertion
Are wires plannable?
Assessment of 3D interconnect geometry at the system level
Modeling and determination of parasitics in submicron VLSI layouts
Derivation of dataflow networks for a domain specific applications
Derivation of a process network for the Jacobium processor
