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GS Garcea
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11 records found
Modeling and determination of parasitics in submicron VLSI layouts
Report -
N.P. van der Meijs
,
A.J. van Genderen
,
GS Garcea
,
S. de Graaf
,
P.M.R.J.O. Dewilde
Derivation of a process network for the Jacobium processor
Conference paper -
GS Garcea
,
B Kienhuis
Buffer planning for global wires under statistical process variations
Conference paper -
GS Garcea
,
N.P. van der Meijs
,
RHJM Otten
Analytic model for area and power constrained optimal repeater insertion
Conference paper -
GS Garcea
,
N.P. van der Meijs
,
RHJM Otten
Trade-offs in buffer planning
Doctoral thesis -
GS Garcea
Derivation of dataflow networks for a domain specific applications
Conference paper -
GS Garcea
Simultaneous analytic area and power optimization for repeater insertion
Conference paper -
GS Garcea
,
N.P. van der Meijs
,
RHJM Otten
Analytic model for area-constrained optimal repeater insertion
Conference paper -
GS Garcea
,
N.P. van der Meijs
,
RHJM Otten
Are wires plannable?
Conference paper -
RHJM Otten
,
GS Garcea
Assessment of 3D interconnect geometry at the system level
Conference paper -
GS Garcea
,
N.P. van der Meijs
Throughput driven unidirectional bus design for NoC applications
Conference paper -
GS Garcea
,
N.P. van der Meijs