This report describes the design and implementation of an interface subsystem for a fall detection system using a pressure based floor sensor. The goal of the fall detection system is to detect and alarm when an elderly person has fallen. The subsystem covers communication between hardware and software, using the WiFi protocol MQTT. The communication is fast enough so that it does not limit other subsystem performance and allows for high expandability to accommodate the hardware’s modular design. The interface module receives a probability of fall occurrence from the separate processing module, from which an average is taken over a 30 second time window to avoid false positives. Alarming is done through the use of text-to-speech voice API to make automated phone calls that retrieve user input to confirm or deny that help is on the way. A habit tracker proof of concept is provided that could improve the accuracy of fall detection by checking if the client is showing anomalies during a given day. A user interface is implemented using the Kivy environment. This environment has its own language which allows for separation of functionality and layout, which keeps the interface elements separate and leads to ease of use. Overall, this results in a strong alternative for fall detection that could be used to improve the time an elderly person can live at home safely without the need to move to a nursing home.

The increasing advancements in quantum computing have led to an increasing danger for the cyberspace. The current cryptographic algorithms that are used to enable secure communication across insecure channels have the potential to be brute-forced by sufficiently powerful quantum computers, endangering the security of many electronic devices and protocols that use popular algorithms such as RSA. Although it is not feasible currently, these advancements in quantum computing are accelerating rapidly and the impact this could have on the security of the cyberspace is too great, therefore countermeasures must be considered. To protect against this threat, the National Institute of Standards and Technology (NIST) has started an initiative to work towards standardizing quantum-resistant cryptoschemes before the advancements in quantum computing reach such a level. This has led to a great amount of collaboration by researchers to develop and analyze the security of these quantum-proof schemes over the past six years. This thesis explores the various post-quantum cryptoschemes that are currently being considered, outlining their differences and the potential advantage of using each scheme. While all of the current submissions are required to have a software implementation to be part of the submission, this is not the case for a hardware implementation. Hardware implementations can have different vulnerabilities than software implementations and, due to this, having one or preferably multiple hardware implementations available for these schemes would greatly advance the security analysis that can be performed for these candidates. Therefore, this thesis describes the hardware implementation process of one such scheme, NTRU, one of the longest standing lattice-based schemes, since this danger of quantum computing is equally dangerous for the many hardware devices and chips that are used worldwide. It discusses the various design decisions that have been made during the implementation and presents all functions that have been implemented to perform the encryption and decryption step of the deterministic public key encryption (DPKE) algorithm of NTRU. This implementation combines work that has been done for the previous NTRU submissions and adds additional logic to support the new and adjusted parts of the current NTRU algorithm. The results show a fully functional encryption and decryption functionality of the NTRU cryptoscheme where the full encryption function can be performed in 3038 clock cycles while still maintaining a considerably low area usage, showing a speedup of 16 when compared to an optimized software implementation. Aside from this result, this thesis also provides several potential adjustments to the hardware implementation that can be made to reduce the decryption time at the cost of additional area so that the hardware can be tuned depending on the desired specifications.