SP

Sara Pellegrini

2 records found

Authored

A multipurpose monolithic array of 2×2 multi-channel digital silicon photomultipliers (MD-SiPMs) fabricated in 40nm CMOS technology is presented. Each MD-SiPM comprises 64×64 smart pixels connected to 128 low-power 45ps sliding-scale time-to-digital converters (TDCs). The MD-SiPM ...

We present a complete pixel based on a singlephoton avalanche diode (SPAD) fabricated in a backsideilluminated (BSI) 3D IC technology. The chip stack comprises an image sensing tier produced in a 65 nm image sensor technology and a data processing tier in 40 nm CMOS. Using a s ...