A High-PDE, Backside-Illuminated SPAD in 65/40 nm 3D IC CMOS Pixel with Cascoded Passive Quenching and Active Recharge

Abstract

We present a complete pixel based on a singlephoton avalanche diode (SPAD) fabricated in a backsideilluminated (BSI) 3D IC technology. The chip stack comprises an image sensing tier produced in a 65 nm image sensor technology and a data processing tier in 40 nm CMOS. Using a simple, CMOS-compatible technique, the pixel is capable of passive quenching and active recharge at voltages well above those imposed by a single transistor whilst ensuring that the reliability limits across the gate-source (VGS), gate-drain (VGD) and drain-source (VDS) are not exceeded for any device. For a given technology, the circuit extends the maximum excess bias that SPADs can be operated at when using transistors as quenching elements, thus improving the SPAD sensitivity, timing performance and photon detection probability (PDP) uniformity. Implemented with 2.5 V thick oxide transistors and operated at 4.4 V excess bias, the design achieves a timing jitter of 95 ps FWHM, maximum photon detection efficiency (PDE) of 21.9% at 660 nm and 0.08% afterpulsing probability with a dead time of 8 ns. This is both the lowest afterpulsing probability at 8 ns dead time and the highest peak PDE for a BSI SPAD in a 3D IC technology to date.