Spur-free all-digital PLL in 65 nm for mobile phones

A novel approach for mitigation of RF oscillator pulling in a polar transmitter

Mismatch considerations in an RF-DAC design for a digital polar EDGE transmitter

Spur-free multirate all-digital PLL for mobile phones in 65nm CMOS

Built-in measurements in low-cost digital-RF transceivers

Digitally controlled oscillator in a 65nm GSM/EDGE transceiver with built-in compensation for capacitor mismatches

A 0.8 mm^2 all-digital SAW-less polar transmitter in 65 nm EDGE SoC

Self-calibration of a Digital Pre-Power Amplifier in a Polar Transmitter

Software assisted digital RF processor (DRP^TM) for single-chip GSM radio in 90 nm CMOS

An efficient linearization scheme for a digital polar EDGE transmitter

A statistical approach for design and testing of analog circuitry in low-cost SoCs

An EDGE transmitter with mitigation of oscillator pulling