Automated hybrid interconnect design for FPGA accelerators using data communication profiling

High-level synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain

Heterogeneous hardware accelerators interconnect: an overview

Heterogeneous hardware accelerators interconnect: an overview

Hybrid interconnect design for heterogeneous hardware accelerators

Heterogeneous hardware accelerator architecture for streaming image processing

Rule-based data communication optimization using quantitative communication profiling

A heuristic-based communication-aware hardware optimization approach in heterogeneous multicore systems