Trade offs in the design of a router with guaranteed and best-effort services for networks on chip

A inified approach to mapping and routing on a network-on-chip for both best-effort and guaranteed service traffic

A buffer-sizing algorithm for networks in chip using TDMA and credit-based end-to-end flow control

A methodology for mapping multiple use-cases onto networks on chips

Mapping and configuration methods for multi-use-case networks on chips

Transaction monitoring in networks on-chip: the on-chip run-time perspective

Low-cost task scheduling for distributed-memory machines

CPR: Mixed Task and Data Parallel Scheduling for Distributed Systems.

Compile-time scheduling for distributed-memory systems

CPR: mixed task and data parallel scheduling for distributed systems

A low-cost approach towards mixed task and data parallel scheduling

Preemptive task scheduling for distributed systems

The distributed ASCI supercomputer project

Fast and effective task scheduling in heterogeous systems

The distributed ASCI supercomputer project

LLB: a fast and effective scheduling algorithm for distributed-memory systems

Improving processor selection complexity in list scheduling algorithms

On the complexity of list scheduling algorithms for distributed-memory systems

List scheduling complexity revisited

FLB: Fast Load Balancing for distributed-memory machines