J.M. Weber
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14 records found
1
Efficient Embedded mmWave Human Pose Estimation
The Effects of Component Size on Model Accuracy, Latency and Memory Usage
In this paper, we create an optimised mmWave human-pose estimation model that runs more accurately without a GPU compared to a baseline model. We do this by analysing a baseline model to find which parts can be compressed without excessively losing accuracy.
Our improved model has an inference time of 41 ms with a Mean Absolute Error (MAE) of 7.72 cm on an embedded device. Compared to the baseline, this model saves 85.9% latency, at the cost of 4.8% MAE accuracy.
Through finding which parts can be compressed most effectively, we also gain insight into the relative importance of each component of the model. We also identify components that, with further research, could be improved to increase the accuracy of the model. ...
In this paper, we create an optimised mmWave human-pose estimation model that runs more accurately without a GPU compared to a baseline model. We do this by analysing a baseline model to find which parts can be compressed without excessively losing accuracy.
Our improved model has an inference time of 41 ms with a Mean Absolute Error (MAE) of 7.72 cm on an embedded device. Compared to the baseline, this model saves 85.9% latency, at the cost of 4.8% MAE accuracy.
Through finding which parts can be compressed most effectively, we also gain insight into the relative importance of each component of the model. We also identify components that, with further research, could be improved to increase the accuracy of the model.
Database-Guided Program Synthesis of Chemical Reaction Networks
Where Reaction-Database Knowledge is most effective in reducing search
...
Efficient mmWave Point-Clouds for Embedded Devices
Evaluating Real-Time Performance of Embedded Millimeter-Wave Radar Pre-Processing Pipelines
This thesis profiles the memory footprint and latency of executing mmWave point-cloud pre-processing on micro-controllers, specifically an STM32 Cortex-M7 with 320 KB of SRAM with the goal of real-time performance by processing each data sample in under 100 ms.
We propose and evaluate seven pipeline variants, incorporating hardware-acceleration, lightweight alternative algorithms, pipeline restructuring to eliminate computational redundancies, and a single-pass iteration strategy to minimize cache misses. Experimental results demonstrate that structural optimization compresses peak memory consumption from 90 KB to 50 KB, successfully approaching the theoretical lower bound dictated by the output buffers. Our most highly optimized configuration achieves an exceptional average latency of 8.13 ms (with a worst-case peak of 12 ms), comfortably satisfying our real-time constraints.
Further analysis revealed that the average point count per frame is the primary driver of computational performance. Ultimately, this work validates that efficient, real-time end-to-end radar processing is entirely viable on highly resource-constrained micro-controllers. ...
This thesis profiles the memory footprint and latency of executing mmWave point-cloud pre-processing on micro-controllers, specifically an STM32 Cortex-M7 with 320 KB of SRAM with the goal of real-time performance by processing each data sample in under 100 ms.
We propose and evaluate seven pipeline variants, incorporating hardware-acceleration, lightweight alternative algorithms, pipeline restructuring to eliminate computational redundancies, and a single-pass iteration strategy to minimize cache misses. Experimental results demonstrate that structural optimization compresses peak memory consumption from 90 KB to 50 KB, successfully approaching the theoretical lower bound dictated by the output buffers. Our most highly optimized configuration achieves an exceptional average latency of 8.13 ms (with a worst-case peak of 12 ms), comfortably satisfying our real-time constraints.
Further analysis revealed that the average point count per frame is the primary driver of computational performance. Ultimately, this work validates that efficient, real-time end-to-end radar processing is entirely viable on highly resource-constrained micro-controllers.
The resulting grammar reproduces the same ringless molecule sets as the legacy baseline on the audited tests and benchmarks, and all generated molecules pass the repository’s valence-validity checks. Runtime results are mixed: on the small water benchmark, the new grammar becomes faster from depth 5 onward and reaches a 2.87× speedup at depth 10, while on methane and urea it remains slower throughout the measured ringless depth series. A fixed-count methane benchmark shows that this slowdown is not mainly caused by legacy validity checking, but by the added search overhead of the larger valence-aware grammar.
The main conclusion is that the new grammar preserves the audited ringless output behaviour while shifting pruning earlier in the search, but this does not translate into consistent runtime gains. ...
The resulting grammar reproduces the same ringless molecule sets as the legacy baseline on the audited tests and benchmarks, and all generated molecules pass the repository’s valence-validity checks. Runtime results are mixed: on the small water benchmark, the new grammar becomes faster from depth 5 onward and reaches a 2.87× speedup at depth 10, while on methane and urea it remains slower throughout the measured ringless depth series. A fixed-count methane benchmark shows that this slowdown is not mainly caused by legacy validity checking, but by the added search overhead of the larger valence-aware grammar.
The main conclusion is that the new grammar preserves the audited ringless output behaviour while shifting pruning earlier in the search, but this does not translate into consistent runtime gains.
Extending AIfES with Depthwise Convolution
Implementation and Evaluation of Depthwise Convolution on Microcontrollers
This project extends AIfES with support for depthwise convolution and integrates the new operator into the existing training pipeline. The implementation was validated using a combination of manually verified test cases, comparisons with TensorFlow, and image classification experiments on embedded hardware. The results show that the new operator functions correctly during both inference and training. Models containing the implemented layer successfully learned classification tasks and achieved behavior similar to equivalent TensorFlow models. By adding support for depthwise convolution, this work expands the range of neural network architectures that can be trained directly on microcontrollers and contributes to making on-device AI more practical and flexible. ...
This project extends AIfES with support for depthwise convolution and integrates the new operator into the existing training pipeline. The implementation was validated using a combination of manually verified test cases, comparisons with TensorFlow, and image classification experiments on embedded hardware. The results show that the new operator functions correctly during both inference and training. Models containing the implemented layer successfully learned classification tasks and achieved behavior similar to equivalent TensorFlow models. By adding support for depthwise convolution, this work expands the range of neural network architectures that can be trained directly on microcontrollers and contributes to making on-device AI more practical and flexible.
Low power event detection on microcontrollers
An Empirical Evaluation and Hierarchical Sensing Pipeline
Inverse Reinforcement Learning (IRL) in Presence of Risk and Uncertainty Related Cognitive Biases
To what extent can IRL learn rewards from expert demonstrations with loss and risk aversion?
What are the implications of Curriculum Learning strategy on IRL methods?
Investigating Inverse Reinforcement Learning from Human Behavior