Wafers in crystalline silicon photovoltaics have grown steadily thinner, and there is reason for that trend to continue. Thinner wafers mean less embodied energy during manufacturing, the efficiency optimum for silicon lies below the thickness currently in use, and a sufficiently thin wafer becomes flexible enough for applications that rigid modules cannot serve. Silicon heterojunction cells are well suited to this, since their excellent surface passivation means the gains from removing bulk material are not swamped by losses at the interfaces. Below 100 µm, however, the difficulty has less to do with efficiency and more with production yield. The wafer no longer behaves as a rigid substrate, and processes designed for thicker substrates begin to break it. This thesis develops a route to ultra-thin silicon heterojunction cells at a wafer thickness of 70 µm, and documents the practical challenges encountered at each step. A thinning process was established that raised the batch size from three wafers to thirteen and simultaneously addressed the breakage mechanisms, by identifying unintended contact as the common cause and changing the wafer holder accordingly. The weighing method of thickness estimation was validated against cross-sectional electron microscopy, and the contribution of the surface texture to the inferred thickness was quantified so that a target bulk thickness could be set with greater accuracy. The intrinsic passivation layer was then optimised for flat (100) surfaces by holding the total thickness fixed and varying the thickness split between the two sub-layers. The hydrogen plasma treatment was tested on flat samples and was found to improve effective lifetime and implied open-circuit voltage on every composition tested. The optimum identified on flat surfaces did not transfer to textured ones, where the standard recipe performed better, so two recipes were carried forward. Working devices were obtained at 70 µm through the complete fabrication sequence. Thinning cost only a moderate amount of short-circuit current, indicating that the retextured surface retains its light-trapping function at this thickness. A single-side texturing route using a silicon nitride mask was also developed, although the cells built on it did not perform. Metallisation of the warped ultra-thin substrates was the principal yield-limiting step in this work, and is identified as the process requiring attention before wafers of this thickness can be handled reliably.