A 5.9 GHz RFDAC-based outphasing power amplifier in 40-nm CMOS with 49.2% efficiency and 22.2 dBm power

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A 5.9 GHz RFDAC-based outphasing power amplifier in 40-nm CMOS with 49.2% efficiency and 22.2 dBm power

Conference Paper (2016)

Author(s)

Z. Hu (TU Delft - Electrical Engineering, Mathematics and Computer Science, University of Electronic Science and Technology of China)

L.C.N. de Vreede (TU Delft - Electrical Engineering, Mathematics and Computer Science)

M.S. Alavi (TU Delft - Electrical Engineering, Mathematics and Computer Science)

D.A. Calvillo-Cortes (TU Delft - Electrical Engineering, Mathematics and Computer Science, Qualcomm Technologies, Inc.)

R.B. Staszewski (TU Delft - Electrical Engineering, Mathematics and Computer Science)

S. He (University of Electronic Science and Technology of China)

Research Group

Electronics

Chireix combiner CMOS Modulation Loading CMOS integrated circuits Power generation Bandwidth Complementary metal oxide semiconductor CMOS power amplifier Switches Radiofrequency power amplifiers Size 40 nm Class-E Dynamic range RFDAC Digital-analogue conversion Differential amplifiers RFDAC-based outphasing power amplifier ROPA drain Differential quasiload-insensitive class-E branch PA Digital amplitude control word Efficiency 49.2 percent Frequency 5.9 GHz Power back-off Radiofrequency digital-to-analog converter Segmentation technique Word length 3 bit Outphasing power amplifier

DOI related publication

https://doi.org/10.1109/RFIC.2016.7508287 Final published version

To reference this document use

https://resolver.tudelft.nl/uuid:01eae8ca-034d-415a-b2b2-46581ebddc89

More Info

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Publication Year

2016

Language

English

Research Group

Electronics

Pages (from-to)

206-209

ISBN (print)

978-1-4673-8652-4

ISBN (electronic)

978-1-4673-8651-7

Event

RFIC 2016 (2016-05-22 - 2016-05-24), San Francisco, CA, United States

Downloads counter

222

Abstract

In this paper, we present a fully integrated RFDAC-based outphasing power amplifier (ROPA) in 40-nm CMOS that achieves 22.2 dBm peak output power with 49.2% drain efficiency at 5.9 GHz. It employs differential quasi-load-insensitive Class-E branch PAs that can dynamically be segmented using a 3-bit digital amplitude control word to improve efficiency at power back-off. At 8 dB back-off, this segmentation technique improves the ROPA drain and system efficiency by 5% and 7%, respectively, when compared to a non-segmented approach.