Thermal Analysis of Cu Pillars
D.X. Desouza (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Guo Qi Zhang – Mentor (TU Delft - Electronic Components, Technology and Materials)
Henk W. van Zeijl – Mentor (TU Delft - Electronic Components, Technology and Materials)
René van den Berg – Mentor (NXP Semiconductors)
Nick Thomassen – Mentor (NXP Semiconductors)
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Abstract
THERMAL management is a very crucial step to ensure the reliability of Integrated Circuits (IC)s. The increase in power density has resulted in the formation of multiple, high-intensity, and non-uniform hotspots. This has not only affected the lifetime but also the performance of several devices. Optimization of the package design and layout are the methods investigated to solve this problem. In flip-chip packaging, each IC product varies with respect to power densities, die area, pin-count, laminate and PCB layers, etc. It is therefore important in understanding how the arrangement and geometry of each layer (in particular the interconnect layer) impacts the overall thermal management.