A 7-Channel Code-Multiplexed Analog CMOS Front-End using an On-Chip Orthogonal Walsh Hadamard Sequence Generator

Abstract

The recording of biosignals, such as atrial electrograms (AEG), electrocardiograms (ECG), and electroencephalograms (EEG), is progressing towards the adoption of more dense electrode arrays in order to improve spatial and temporal resolution. The proliferation of channels necessitates some form of channel sharing technique so that efficient low power and area recording can be achieved.
In this thesis, a code-division multiplexed analog front-end is designed due to its efficient use of bandwidth in comparison to time and frequency multiplexing. Orthogonal coding schemes such as Walsh-Hadamard sequences are best suited for minimising cross-talk. These codes are typically implemented using an LUT or processor which becomes a significant overhead when a large number of channels are to be multiplexed. However, by investigating the sequences closely, a novel method of generating these codes from a clock signal using digital logic was devised. The proposed algorithm to generate these sequences on-chip provides significant area savings for sequences of length greater than 8, which makes the design scalable for a large number of channels,. The reduction in area ranges from a factor of 10 for a code length of 8 up to a factor as large as 200 for a code length of 128.
As orthogonal sequences require a low bandwidth, a low bandwidth low-noise amplifier and ADC were used for amplification and digitisation of the signal. By using digitally inspired analog blocks, such as an inverter-based amplifier, lower power consumption could be achieved.
The entire design was implemented to share 7 channels. The code generator, low-noise amplifier and ADC consume a total of 78.4μW, which corresponds to 11.2μW per channel. This is a 3.3x improvement to the design in [5] where pseudo-random sequences were used as the coding scheme. However, the design consumes more power than a state-of-the-art design reported in [6] which uses 1.97μW per channel. While the design is currently not optimized with respect to power consumption in comparison to the design in [6], the novel code generation technique reported in this thesis makes the design scalable for larger number of channels. This is because the area constraint of the LUT is no more the limiting factor in terms of area.