Carbon Nanotubes as Vertical Interconnects in 3D Integrated Circuits

Abstract

Interconnects in integrated circuits (IC) are the major cause of power dissipation and delay. 3D integration has been proposed as a method to reduce these issues. For this 3D integration, fabrication of high aspect ratio reliable vertical interconnects (vias) are required. For this new materials, like carbon nanotubes (CNT), are being considered due to their excellent electrical and thermal properties. In this thesis CNT are investigated for the use as via in 3D IC. Raman spectroscopy is investigated for determining the CNT quality. CNT are grown on electrically conductive TiN layers at record-low temperatures of 350 °C using Co as catalyst. On electrically conductive ZrN layers CNT bundles with lengths of several hundred micrometre could be grown using Fe as catalyst, which is to our knowledge the first example of ultra-long CNT on a conductive substrate. Electrical measurements were performed on CNT vias fabricated at 350-500 °C. The contact resistance, uniformity, electrical reliability, and resistivity were determined and compared to literature. The resistivity of 20 m?-cm is similar to values in literature, and high compared to that of Cu and Al due to the low quality and bundle density of the CNT. The thermal conductivity of the CNT bundles was also found to be low due to their low quality, and large thermal interface resistance between the CNT and metal. Finally, for the first time CNT were integrated directly with actual electronics, and 3D IC with two transistor layers were fabricated and characterised. The large CNT via resistance due to their low quality was found to limit the performance of the transistors. This indicates that the material properties of CNT should be improved considerably before they can be put to use in actual IC.