Event-Based Simulation of Computing-In-Memory Accelerators
A.L. Herrera Gama (TU Delft - Electrical Engineering, Mathematics and Computer Science)
G. Gaydadjiev – Mentor (TU Delft - Computer Engineering)
T. Spyrou – Mentor (TU Delft - Computer Engineering)
C.J.M. Verhoeven – Graduation committee member (TU Delft - Electronics)
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Abstract
The hardware demand to accelerate neural network inference in the context of machine learning (ML) and artificial intelligence (AI) has been rapidly growing. Complex models and the widespread use of AI in various domains have led to the problem of energy budget for AI in datacenters becoming a critical problem. The primary contributor is the frequent data movement between memory and processing units, requiring new computing paradigms supporting fast yet energy-efficient neural network inference. Computing-in-Memory (CIM) addresses the “memory wall” of von Neumann architectures by performing parallel computations directly in the memory array. Various memory technologies, including emerging non-volatile memories (NVMs) such as RRAM, FeRAM, PCRAM, STT-MRAM, and optimised structures of conventional SRAM, have been explored for CIM applications.
Designing CIM systems requires multi-level simulation approaches because device or circuit-level design choices can significantly impact system-level efficiency and accuracy. Simulations for CIM architectures span a broad spectrum, from high-level analytical models that provide quick but coarse estimates to detailed circuit-level simulations that provide accuracy at the cost of scalability. However, this leaves a gap in evaluating CIM architectures at realistic workload scales while maintaining sufficient fidelity. This work targets the intermediate cycle- and system-level domain to address this, aiming to bridge the gap between abstract analytical evaluations and low-level hardware description implementations.
This work develops an event-based CIM architecture simulation framework showcased by the simulation of an accelerator system defined with a target multiply and accumulate (MAC) block architecture. Workloads, including basic MLP, CNN, and NLP models, were executed to analyse metrics such as cycle delay, tile count and utilisation as an efficiency indicator. The impact of tunable simulation parameters was also evaluated considering four defined MAC block topologies. Simulation results show for an MLP workload an increase of 7.6% tile utilisation between two topologies, while reporting on both the number of execution cycles and necessary hardware.
Overall, the CIM architecture simulation platform can effectively serve as a tool for mid-stage design exploration and performance evaluation of CIM-based accelerators. The framework’s modular, eventbased structure enables architectural exploration while providing realistic timing behaviour, distinguishing it from analytical and device-level tools.