Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads

Journal article (2017)

Authors

D.H.P. Kraak Computer Engineering - EEMCS
M. Taouil Computer Engineering - EEMCS
I.O. Agbo Computer Engineering - EEMCS
S. Hamdioui Computer Engineering - EEMCS
Pieter Weckx Katholieke Universiteit Leuven, IMEC
Francky Catthoor Katholieke Universiteit Leuven, IMEC
Research Group
Computer Engineering (EEMCS) (TU Delft)
Mitigation Aging Sense amplifier (SA) Memory Offset voltage Static random-access memory Time-dependent variability Time-zero variability
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Published Date

2017

Language

English

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering

Abstract

Designers typically add design margins to compensate for time-zero variability (due to process variation) and time-dependent (due to, e.g., bias temperature instability) variability. These variabilities become worse with scaling, which leads to larger design margin requirements. As an alternative, mitigation schemes can be applied to counteract the variability. This paper investigates the impact of aging on the offset voltage of the memory's sense amplifier (SA). For the analysis, the degradation of the SAs in the L1 data and instruction caches of an ARM processor is quantified while using realistic workloads extracted from the SPEC CPU2006 Benchmark suite. Furthermore, the effect of our mitigation scheme, i.e., an online control circuit that balances the SA workload, is analyzed. The simulation results show that the mitigation scheme reduces the offset voltage degradation due to aging with up to 40% for the benchmarks, depending on the stress conditions (temperature, voltage, and workload).

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