Testing of Interconnect and Contact Defects in STT-MRAMs
Z. ZHANG (TU Delft - Electrical Engineering, Mathematics and Computer Science)
S. Hamdioui – Mentor (TU Delft - Quantum & Computer Engineering)
M. Taouil – Mentor (TU Delft - Computer Engineering)
A. Bossche – Graduation committee member (TU Delft - Electronic Instrumentation)
More Info
expand_more
Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.
Abstract
Spin-transfer-torque magnetic random access memory (STT-MRAM) is regarded as one of the most promising non-volatile memory (NVM) technologies, which has the potential to replace the traditional memories in the modern memory hierarchy. Due to some advantages such as non-volatility, fast access speed, low leakage power and high density, more and more research attention is being paid to STT-MRAM. To enable the mass production of STT-MRAM, high-quality and cost-efficient test solutions are the prerequisites. In this thesis, the comprehensive investigation for testing interconnect and contact defects in STT-MRAMs will be presented. The complete defect space for interconnect and contact defects in STT-MRAMs is systematically defined, which are modelled as linear resistors. All theoretically possible faults are defined in a fault space, followed by a methodology to validate these faults under inter-cell magnetic coupling in the presence of defined defects. In this way, accurate fault modelling is performed to guarantee the occurrence of realistic faults in STT-MRAMs. We observed the specific STT-MRAM fault model—passive neighborhood pattern sensitive fault (PNPSF). Based on the fault validation results, an effective march test algorithm(7N) is proposed for interconnect and contact defects in STT-MRAMs.