Precise and Fast Simulation of RRAM Crossbar Arrays
The design and implementation of a fast simulation framework for resistive memristor-based computation in memory crossbar arrays
B. Smeele (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Georgi Gaydadjiev – Mentor (TU Delft - Computer Engineering)
T. Spyrou – Mentor (TU Delft - Computer Engineering)
M. Möller – Graduation committee member (TU Delft - Numerical Analysis)
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Abstract
This thesis presents a RRAM-crossbar simulation framework aimed at precise and fast simulation.
Specifically, the model simulates a memristive crossbar with parasitic wire resistances, generating output currents and tracking the internal memristive states based on applied input voltages. Implemented in C++, the developed model has a clear interface making it suitable for integration into larger simulation frameworks for CIM-based accelerators. Experimental results demonstrate that the simulator is significantly faster than Cadence Spectre, while maintaining sufficient accuracy for use in behavioral-level CIM simulations.
The complete model is divided into three sub-modules: a memristor model, a linear crossbar model, and a non-linear crossbar model. The memristor model is based on the JART VCM v1b var model by Bengel et al. [2], and its implementation is a faithful translation of the associated Verilog-A code [3], with additional functionality for simulation in C++. Additionally, other memristor models can be implemented through an abstract memristor class.
Experimental results show that the developed simulation framework is significantly faster than Cadence Spectre while retaining a relative error below 1%. Additionally, the crossbar and the memristors are modeled to more closely reflect physical device behaviour than in other RRAM simulation frameworks. Finally, a study of linear and non-linear memristor simulation in a crossbar shows a measurable difference, suggesting approximating memristors as linear impacts simulation accuracy