Atomistic-level hysteresis-aware graphene structures electron transport model

Conference Paper (2019)
Authors

He Wang (TU Delft - Computer Engineering)

N. Cucu Laurenciu (TU Delft - Computer Engineering)

Yande Jiang (TU Delft - Computer Engineering)

Shao Ku Kao Cotofana (TU Delft - Computer Engineering)

Research Group
Computer Engineering
To reference this document use:
https://doi.org/10.1109/ISCAS.2019.8702106
More Info
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Publication Year
2019
Language
English
Research Group
Computer Engineering
Volume number
2019-May
Pages (from-to)
1-5
ISBN (electronic)
9781728103976
DOI:
https://doi.org/10.1109/ISCAS.2019.8702106

Abstract

Hysteretic behavior has been experimentally observed in graphene-based structures and has a major influence on graphene surface potential and gate field modulation ability. Thus, a graphene electronic transport modelling methodology, which incorporates hysteresis effects is crucial in order to properly assess gated-controlled graphene structures response and performance. To this end, we propose an atomistic-level electronic transport model, which is non restricted to rectangular graphene geometries and captures hysteretic effects caused by near-interfacial traps, provided that interface traps trapping/detrapping time constant and density are known. We apply the model on a rectangular graphene shape and validate our results against experimentally measured drain current vs. top gate voltage hysteresis curves. Moreover, to demonstrate model's versatility we consider two non-rectangular Graphene NanoRibbons (GNRs) and investigate their hysteresis behaviour. Our experiments indicate good agreement between simulated and measured results, which qualifies the model appropriate for traps-aware exploration of the conduction behaviour of graphene-based devices and circuits.

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