Controll processors for CIM accelerators

Abstract

To address the “memory wall” of von Neumann architectures, computation-in-memory (CIM) emerges as a promising paradigm that performs computation directly within memory, thereby enhancing energy efficiency and performance by minimizing data movement. This thesis explores a CIM tile architecture for 1T1R memristor crossbar arrays, supporting fundamental operations including write, read, verification, logic (AND, OR, XOR), and vector-matrix multiplication (VMM). The proposed design integrates key components including input/output buffers, analog interfaces such as Digital-to-Input Modules, Sample&Hold modules, and Analog-to-Digital Converters (ADCs), as well as a comprehensive digital periphery. The digital periphery encompasses the Column Selection, Row Selection, Row Data Selection, and Spare Row Selection modules, Logical Unit, Verification Unit, Read Register, and threestage Addition Unit dedicated to VMM.
A significant part of our work is the RTL design and gate-level implementation of the tile’s comprehensive digital periphery. As part of this effort, we design and implement a novel Verification Unit that performs offline validation of data written to the crossbar array. This unit detects write errors, initiates selective rewriting of faulty cells, and performs re-verification. If a failure persists, it automatically flags the affected row, disables it for future computations, and triggers remapping to a spare row. Furthermore, we develop analytical models for estimating the area and energy consumption of the digital periphery, based on the characterized gate-level implementation.
The remapping functionality is validated through RTL simulation and the gate-level implementation of the tile’s comprehensive digital periphery is evaluated through post-synthesis simulations using Cadence Genus. We analyze area and energy consumption across key architectural parameters including crossbar size, number of ADCs, operand width, number of spare rows, external bus width, and WDS/RDS instruction data field width. Area analysis shows linear growth with crossbar size and spare rows, non-monotonic relationship with operand width (first decreasing then increasing), increasing trend with ADC count, and inverse relationships with bus width and data field width. Energy analysis reveals that store operations exhibit quadratic scaling with crossbar size and inverse proportionality with bus width;verification, read, and logic operations show quadratic scaling with crossbar size and inverse relationships with ADC count; VMM operations display linear scaling with crossbar size, inverse relationship with ADC count, and inverse proportionality with WDS/RDS instruction data field width. These findings provide valuable guidance for parameter optimization in CIM tile design.