Challenges and Solutions in Emerging Memory Testing

Journal Article (2019)
Author(s)

E.I. Vatajelu (Université Grenoble Alpes)

Paolo Prinetto (CINI Cybersecurity National Lab, Politecnico di Torino)

Mottaqiallah Taouil (TU Delft - Computer Engineering)

Said Hamdioui (TU Delft - Computer Engineering)

Research Group
Computer Engineering
Copyright
© 2019 E.I. Vatajelu, Paolo Prinetto, M. Taouil, S. Hamdioui
DOI related publication
https://doi.org/10.1109/TETC.2017.2691263
More Info
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Publication Year
2019
Language
English
Copyright
© 2019 E.I. Vatajelu, Paolo Prinetto, M. Taouil, S. Hamdioui
Research Group
Computer Engineering
Issue number
3
Volume number
7
Pages (from-to)
493-506
Reuse Rights

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Abstract

The research and prototyping of new memory technologies are getting a lot of attention in order to enable new (computer) architectures and provide new opportunities for today’s and future applications. Delivering high quality and reliability products was and will remain a crucial step in the introduction of new technologies. Therefore, appropriate fault modelling, test development and design for testability (DfT) is needed. This paper overviews and discusses the challenges and the emerging solutions in testing three classes of memories: 3D stacked memories, Resistive memories and Spin-Transfer-Torque Magnetic memories. Defects mechanisms, fault models, and emerging test solutions will be discussed.

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