Performance and surge capacity evaluations of 1.2kV SiC VDMOSFETs with varied JFET width

Abstract

The 1.2 kV SiC VDMOSFETs with varied JFET width (LJFET) are designed and fabricated in this study. The static and dynamic characteristics of each design are measured and compared. There is the best trade-off performance in the design of LJFET = 1.8 μm according to FOM (BV2/Ron) and FOM (Ciss/Crss). Besides, the surge capacity and evaluation for series designs are investigated under conditions of Vgs = 0 V and Vgs = −5 V. There is a best surge capacity in design of LJFET=1.2 μm, and the largest surge energy is the design of LJFET=2.0 μm. Further, the surge failure mechanisms of LJFET = 1.2 μm, 1.8 μm, and 2.0 μm under condition of Vgs = −5 V are investigated by decapsulated and FIB. Besides, the TCAD simulation was employed to theoretical analysis. The results show that the extremely high temperature was generated instantaneously under surge condition, resulting in epoxy carbonization, polysilicon melting and ILD oxide crack in failed position. Besides, the surge dissipating energy causes an instantaneous high temperature on the entire chip, resulting in aluminum remetallization. This paper would provide suggestions for device design and surge study.