Optimizing Compiler for Neuromorphic Hardware

Abstract

The rapid advancement of neural network applications, including multilayer perceptrons (MLP) and deep convolutional neural networks (CNN), has revolutionized domains such as image recognition, speech processing, and classification. However, the increasing depth and complexity of neural network workloads impose significant computational and energy demands. Conventional hardware, such as CPUs and GPUs, faces growing challenges in meeting these demands due to the "memory wall" problem and the diminishing benefits of Moore’s law and Dennard scaling. These issues are particularly pronounced in edge devices where power and energy efficiency are critical.

To address these limitations, computing-in-memory (CIM) architectures, particularly memristor-based crossbar arrays, have emerged as promising solutions. CIM reduces data movement by performing computations directly within memory, significantly improving energy efficiency and performance. Memristor crossbars excel in analog matrix-vector multiplication (MVM), a fundamental operation in neural networks, making them an ideal candidate for accelerating neural network workloads.

This thesis proposes an end-to-end compilation framework that automates the translation and optimization of neural networks for CIM architectures. The framework supports converting high-level MLP models represented in PyTorch into low-level instructions optimized for crossbar-based spatial CIM architectures. Comprehensive experiments explore the impact of various quantization schemes and design space parameters, revealing trade-offs between performance, energy efficiency, and resource utilization. The results demonstrate the framework's potential to support diverse neuromorphic systems and facilitate the efficient deployment of neural networks on CIM architectures.