Periphery-Aware Power Side-Channel Hardening for Digital CIM-BNN Accelerators

Abstract

Mapping Binary Neural Networks (BNNs) on computation-in-memory (CIM) architectures enables a highly efficient approach for energy-constrained edge computing. In-memory processing significantly reduces critical performance bottlenecks in conventional architectures. Despite their efficiency, current optimized CIM implementations remain vulnerable to IP theft via side-channel analysis. This work investigates the side-channel leakage of a digital BNN-CIM accelerator that employs popcount-based accumulation. A range of circuit-level modifications in counter implementations are proposed and evaluated, exploring their impact on security metrics and design overhead. Results demonstrate that the Hamming weight (HW) and Hamming distance (HD) equalizing techniques combined with power equalization through duplication perform better than traditional dual-rail countermeasures. The findings provide practical guidance for designing secure and efficient peripheral components for popcount-based BNN accelerators.