ChiselTrace: Typed Behavioral Debugging in Chisel Through Signal Dependency Tracing

Abstract

While modern HDLs such as Chisel (Constructing Hardware In a Scala Embedded Language) significantly improve the process of design entry, debugging these designs is often problematic, because the tools that aid debugging operate on translated code rather than the original HDL. Furthermore, engineers often resort to manual waveform debugging, undermining productivity gains promised by such a language. We present ChiselTrace, an open-source tool for Chisel that is capable of (dynamic) program slicing and automatic signal dependency tracing, allowing faults to be more easily traced back to their root cause. Where prior work focuses on data-flow analysis at the (compiled) Verilog level, ChiselTrace functions at the Chisel source level. Contributions include: modifications to the Chisel library to enable post-simulation analysis; a library capable of dynamic program slicing and dependence graph generation; and a front-end dependency graph viewer. We demonstrate debugging capabilities by tracing an injected fault in the ChiselWatt processor back to the source. We observe that using ChiselTrace's dynamic program dependence graph, the number of lines of code relevant to the fault path is reduced significantly. Project repository: https://github.com/jarlb/chiseltrace