P-GaAs Nanowire Metal-Semiconductor Field-Effect Transistors with Near-Thermal Limit Gating

Journal Article (2018)
Author(s)

A. R. Ullah (University of New South Wales)

F. Meyer (University of New South Wales)

J. G. Gluschke (University of New South Wales)

S. Naureen (IRnova AB, Kista, Australian National University)

P. Caroff (Microsoft Quantum Lab Delft, TU Delft - QRD/Kouwenhoven Lab)

P. Krogstrup (University of Copenhagen)

J. Nygård (University of Copenhagen)

A. P. Micolich (University of New South Wales)

DOI related publication
https://doi.org/10.1021/acs.nanolett.8b02249 Final published version
More Info
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Publication Year
2018
Language
English
Issue number
9
Volume number
18
Pages (from-to)
5673-5680
Downloads counter
299

Abstract

Difficulties in obtaining high-performance p-type transistors and gate insulator charge-trapping effects present two major challenges for III-V complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs nanowire metal-semiconductor field-effect transistor (MESFET) that eliminates the need for a gate insulator by exploiting the Schottky barrier at the metal-GaAs interface. Our device beats the best-performing p-GaSb nanowire metal-oxide-semiconductor field effect transistor (MOSFET), giving a typical subthreshold swing of 62 mV/dec, within 4% of the thermal limit, on-off ratio ∼105, on-resistance ∼700 kω, contact resistance ∼30 kω, peak transconductance 1.2 μS/μm, and high-fidelity ac operation at frequencies up to 10 kHz. The device consists of a GaAs nanowire with an undoped core and heavily Be-doped shell. We carefully etch back the nanowire at the gate locations to obtain Schottky-barrier insulated gates while leaving the doped shell intact at the contacts to obtain low contact resistance. Our device opens a path to all-GaAs nanowire MESFET complementary circuits with simplified fabrication and improved performance.