We report a method for growing rectangular InAs nanofins with deterministic length, width, and height by dielectric-templated selective-area epitaxy. These freestanding nanofins can be transferred to lay flat on a separate substrate for device fabrication. A key goal was to regain a spatial dimension for device design compared to nanowires, while retaining the benefits of bottom-up epitaxial growth. The transferred nanofins were made into devices featuring multiple contacts for Hall effect and four-terminal resistance studies, as well as a global back-gate and nanoscale local top-gates for density control. Hall studies give a 3D electron density 2.5-5 × 1017 cm-3, corresponding to an approximate surface accumulation layer density 3-6 × 1012 cm-2 that agrees well with previous studies of InAs nanowires. We obtain Hall mobilities as high as 1200 cm2/(V s), field-effect mobilities as high as 4400 cm2/(V s), and clear quantum interference structure at temperatures as high as 20 K. Our devices show excellent prospects for fabrication into more complicated devices featuring multiple ohmic contacts, local gates, and possibly other functional elements, for example, patterned superconductor contacts, that may make them attractive options for future quantum information applications.@en

Selective-area growth is a promising technique for enabling of the fabrication of the scalable III-V nanowire networks required to test proposals for Majorana-based quantum computing devices. However, the contours of the growth parameter window resulting in selective growth remain undefined. Herein, we present a set of experimental techniques that unambiguously establish the parameter space window resulting in selective III-V nanowire networks growth by molecular beam epitaxy. Selectivity maps are constructed for both GaAs and InAs compounds based on in situ characterization of growth kinetics on GaAs(001) substrates, where the difference in group III adatom desorption rates between the III-V surface and the amorphous mask area is identified as the primary mechanism governing selectivity. The broad applicability of this method is demonstrated by the successful realization of high-quality InAs and GaAs nanowire networks on GaAs, InP, and InAs substrates of both (001) and (111)B orientations as well as homoepitaxial InSb nanowire networks. Finally, phase coherence in Aharonov-Bohm ring experiments validates the potential of these crystals for nanoelectronics and quantum transport applications. This work should enable faster and better nanoscale crystal engineering over a range of compound semiconductors for improved device performance.@en

Selective area growth is a promising technique to realize semiconductor-superconductor hybrid nanowire networks, potentially hosting topologically protected Majorana-based qubits. In some cases, however, such as the molecular beam epitaxy of InSb on InP or GaAs substrates, nucleation and selective growth conditions do not necessarily overlap. To overcome this challenge, we propose a metal-sown selective area growth (MS SAG) technique, which allows decoupling selective deposition and nucleation growth conditions by temporarily isolating these stages. It consists of three steps: (i) selective deposition of In droplets only inside the mask openings at relatively high temperatures favoring selectivity, (ii) nucleation of InSb under Sb flux from In droplets, which act as a reservoir of group III adatoms, done at relatively low temperatures, favoring nucleation of InSb, and (iii) homoepitaxy of InSb on top of the formed nucleation layer under a simultaneous supply of In and Sb fluxes at conditions favoring selectivity and high crystal quality. We demonstrate that complex InSb nanowire networks of high crystal and electrical quality can be achieved this way. We extract mobility values of 10000-25000 cm2 V-1 s-1 consistently from field-effect and Hall mobility measurements across single nanowire segments as well as wires with junctions. Moreover, we demonstrate ballistic transport in a 440 nm long channel in a single nanowire under a magnetic field below 1 T. We also extract a phase-coherent length of ∼8 μm at 50 mK in mesoscopic rings.@en

Difficulties in obtaining high-performance p-type transistors and gate insulator charge-trapping effects present two major challenges for III-V complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs nanowire metal-semiconductor field-effect transistor (MESFET) that eliminates the need for a gate insulator by exploiting the Schottky barrier at the metal-GaAs interface. Our device beats the best-performing p-GaSb nanowire metal-oxide-semiconductor field effect transistor (MOSFET), giving a typical subthreshold swing of 62 mV/dec, within 4% of the thermal limit, on-off ratio ∼105, on-resistance ∼700 kω, contact resistance ∼30 kω, peak transconductance 1.2 μS/μm, and high-fidelity ac operation at frequencies up to 10 kHz. The device consists of a GaAs nanowire with an undoped core and heavily Be-doped shell. We carefully etch back the nanowire at the gate locations to obtain Schottky-barrier insulated gates while leaving the doped shell intact at the contacts to obtain low contact resistance. Our device opens a path to all-GaAs nanowire MESFET complementary circuits with simplified fabrication and improved performance.@en

GaAsSb nanowire arrays were grown by gold-seeded metalorganic vapor phase epitaxy (MOVPE) and fabricated into photodetector devices. The array photodetectors operate at room temperature with tunable resonance peaks varying with the array geometry. These devices are promising for multispectral photodetector applications.@en

Recent advances in bottom-up growth are giving rise to a range of new two-dimensional nanostructures. Hall effect measurements play an important role in their electrical characterization. However, size constraints can lead to device geometries that deviate significantly from the ideal of elongated Hall bars with currentless contacts. Many devices using these new materials have a low aspect ratio and feature metal Hall probes that overlap with the semiconductor channel. This can lead to a significant distortion of the current flow. We present experimental data from InAs 2D nanofin devices with different Hall probe geometries to study the influence of Hall probe length and width. We use finite-element simulations to further understand the implications of these aspects and expand their scope to contact resistance and sample aspect ratio. Our key finding is that invasive probes lead to significant underestimation of measured Hall voltage, typically of the order 40-80%. This in turn leads to a subsequent proportional overestimation of carrier concentration and an underestimation of mobility.@en