Recent advances in bottom-up growth are giving rise to a range of new two-dimensional nanostructures. Hall effect measurements play an important role in their electrical characterization. However, size constraints can lead to device geometries that deviate significantly from the ideal of elongated Hall bars with currentless contacts. Many devices using these new materials have a low aspect ratio and feature metal Hall probes that overlap with the semiconductor channel. This can lead to a significant distortion of the current flow. We present experimental data from InAs 2D nanofin devices with different Hall probe geometries to study the influence of Hall probe length and width. We use finite-element simulations to further understand the implications of these aspects and expand their scope to contact resistance and sample aspect ratio. Our key finding is that invasive probes lead to significant underestimation of measured Hall voltage, typically of the order 40-80%. This in turn leads to a subsequent proportional overestimation of carrier concentration and an underestimation of mobility.

We report a method for growing rectangular InAs nanofins with deterministic length, width, and height by dielectric-templated selective-area epitaxy. These freestanding nanofins can be transferred to lay flat on a separate substrate for device fabrication. A key goal was to regain a spatial dimension for device design compared to nanowires, while retaining the benefits of bottom-up epitaxial growth. The transferred nanofins were made into devices featuring multiple contacts for Hall effect and four-terminal resistance studies, as well as a global back-gate and nanoscale local top-gates for density control. Hall studies give a 3D electron density 2.5-5 × 10¹⁷ cm^-3, corresponding to an approximate surface accumulation layer density 3-6 × 10¹² cm^-2 that agrees well with previous studies of InAs nanowires. We obtain Hall mobilities as high as 1200 cm²/(V s), field-effect mobilities as high as 4400 cm²/(V s), and clear quantum interference structure at temperatures as high as 20 K. Our devices show excellent prospects for fabrication into more complicated devices featuring multiple ohmic contacts, local gates, and possibly other functional elements, for example, patterned superconductor contacts, that may make them attractive options for future quantum information applications.

Difficulties in obtaining high-performance p-type transistors and gate insulator charge-trapping effects present two major challenges for III-V complementary metal-oxide semiconductor (CMOS) electronics. We report a p-GaAs nanowire metal-semiconductor field-effect transistor (MESFET) that eliminates the need for a gate insulator by exploiting the Schottky barrier at the metal-GaAs interface. Our device beats the best-performing p-GaSb nanowire metal-oxide-semiconductor field effect transistor (MOSFET), giving a typical subthreshold swing of 62 mV/dec, within 4% of the thermal limit, on-off ratio ∼10⁵, on-resistance ∼700 kω, contact resistance ∼30 kω, peak transconductance 1.2 μS/μm, and high-fidelity ac operation at frequencies up to 10 kHz. The device consists of a GaAs nanowire with an undoped core and heavily Be-doped shell. We carefully etch back the nanowire at the gate locations to obtain Schottky-barrier insulated gates while leaving the doped shell intact at the contacts to obtain low contact resistance. Our device opens a path to all-GaAs nanowire MESFET complementary circuits with simplified fabrication and improved performance.