Improvement on the short-circuit Performance of SiC MOSFET with different shapes and materials of the dielectric layer
Hanshi Wang (Southern University of Science and Technology )
Yifan Lou (Southern University of Science and Technology )
Xiaowei Zhang (Sky Chip Interconnection Technology Co)
Shaogang Wang (TU Delft - Bio-Electronics)
Ke Liu (Southern University of Science and Technology )
Tuobei Sun (Nanjing MoliSemiconductor Co)
Chunjian Tan (Southern University of Science and Technology )
Huaiyu Ye (Southern University of Science and Technology )
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Abstract
In this paper, the effect of thermal stress on the reliability of the gate dielectric layer of SiC MOSFET at high short-circuit temperature is studied. By modeling and simulation, different shapes and materials (SiO2, BPSG, Si3N4) of the dielectric layer were compared regarding their stress distribution effects. Results indicate that elliptical gate structures and dual-layer ILD configurations perform better under thermal stress than conventional designs, particularly with Si3N4 as the inner layer and BPSG as the outer layer. This optimization scheme aims to enhance the reliability of SiC MOSFETs.