Electrowetting for chip assembly

Master Thesis (2024)
Author(s)

K.R. Tack (TU Delft - Mechanical Engineering)

Contributor(s)

M. Tichem – Mentor (TU Delft - Micro and Nano Engineering)

J.F.L. Goosen – Graduation committee member (TU Delft - Computational Design and Mechanics)

Gerard J. Verbiest – Mentor (TU Delft - Dynamics of Micro and Nano Systems)

Faculty
Mechanical Engineering
More Info
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Publication Year
2024
Language
English
Graduation Date
20-12-2024
Awarding Institution
Delft University of Technology
Project
X.AL
Programme
Mechanical Engineering | High-Tech Engineering
Sponsors
Nexperia
Faculty
Mechanical Engineering
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Abstract

This study explores the design and implementation of an electrowetting-on-dielectric (EWOD) system for precise die positioning in a chip assembly environment, utilizing a millimeter-scale ”chip-on-droplet” approach. Two methodologies were investigated: coarse positioning using digital signals, a method well-documented in prior research, and fine positioning using analog signals, which, to the best of our knowledge, had not been applied to droplet positioning at the time of writing. The primary advantage of the fine positioning approach lies in its independence from feature size, allowing for significantly smaller step sizes. Experimental results demonstrated that the analog system achieved step sizes as small as 3.5 μm in a ”droplet only” setup, outperforming the ”traditional” coarse positioning system. Performance limitations were found to arise primarily from the tracking setup rather than the EWOD system itself.
The study also evaluated various surface layers, confirming prior findings that a smooth, thin, and homogeneous surface layer is critical for achieving consistent and precise movement. Attempts to en- hance droplet guidance through modified surface structures were unsuccessful due to pinning forces exceeding the generated EWOD forces. These findings highlight the potential of analog signal-driven EWOD systems for fine positioning applications, with important implications for chip assembly tech- nologies.

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