The PMP Snapshot Engine

Fast and Fault-Resilient PMP Reconfiguration for RISC-V

Conference Paper (2026)
Author(s)

Christian Larmann (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Abdullah Aljuffri (King Abdulaziz City for Science and Technology)

Adrian Marotzke (Nxp Semiconductors)

Alejandro Garza (Nxp Semiconductors)

Said Hamdioui (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Mottaqiallah Taouil (TU Delft - Electrical Engineering, Mathematics and Computer Science)

Research Group
Computer Engineering
DOI related publication
https://doi.org/10.23919/DATE69613.2026.11539331 Final published version
More Info
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Publication Year
2026
Language
English
Research Group
Computer Engineering
Publisher
IEEE
ISBN (electronic)
9783982674117
Event
2026 Design, Automation and Test in Europe Conference, DATE 2026 (2026-04-20 - 2026-04-22), Verona, Italy
Page Views
87
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Abstract

This paper presents a Physical Memory Protection Snapshot Engine (PSE), a lightweight hardware extension for RISC-V that addresses both performance and security challenges of Physical Memory Protection (PMP) reconfiguration. By storing and restoring full PMP configurations in a single cycle, the PSE drastically reduces the overhead of context switches typically used in Trusted Execution Environments (TEEs) and secure real-time systems. At the same time, the redundant storage and two-dimensional parity protection provide an efficient and effective defense against fault injection attacks that target PMP registers. In 100k randomized trials, our experimental results demonstrate that the PSE can reliably detect and prevent FI-induced privilege escalations, while incurring only 11.7% area overhead. This makes it a practical solution for embedded devices where both efficiency and trustworthiness are essential.

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