ESRAM Reliability

Abstract

As technology scales down, the impact of variability due to process variation and aging increases. In order to guarantee an optimal design with a low failure rate, it is crucial to take into account the impact of these sources of variability. Prior work on SRAM reliability has mainly focused on estimating the impact of this variability on the memory cell array, while the peripheral circuitry and the complete memory circuit have received little attention. This study analyzes the impact of aging on a complete 14nm FinFET SRAM circuit. In this analysis, it is investigated how the memory's individual components contribute to the memory's overall degradation. In addition, it is investigated how the application-dependent aging impacts the memory. The results of this work show that, depending on the investigated metric, the peripheral circuitry has a significantly higher contribution to the overall degradation of the memory than the cell array. In addition, the degradation of the memory is shown to be strongly dependent on the application. Overall, the results of this study emphasize that the impact of the peripheral circuitry and the application-dependent aging must be taken into account during design in order to optimally solve SRAM reliability.