Intermediate Flag Verification for Logical Zero State Preparation

Abstract

Logical state preparation is a fundamental step in fault-tolerant quantum computing, and logical |0⟩𝐿 states are frequently needed throughout fault-tolerant circuits, for example at the start of computation, during error correction, or as part of magic state distillation. It is therefore important that they can be implemented efficiently. This thesis investigates intermediate verification (IV) as an alternative strategy, where the verification step is placed partway through the preparation circuit rather than at the end. We use the |0⟩𝐿 state of the [[15, 1, 3]] code as a case study, and construct IV circuits based on the recursive structure of its encoding circuit. We prove that such circuits remain fault-tolerant for punctured quantum Reed-Muller (PQRM) codes of the form PQRM(1, 𝑚−2, 𝑚) with 𝑚 ≥ 4 and 𝑑 = 3, including the [[15, 1, 3]] code as the special case 𝑚 = 4.
We compare IV and final verification circuits under realistic noise models, evaluating their logical error rate, acceptance probability, and expected runtime. Our results show that IV does not always improve expected runtime, since the acceptance probability is already high in the relevant noise regime. How- ever, IV could lead to reduced circuit depth after native gate compilation and scheduling. Hardware experiments on the Quantinuum H1-1 trapped-ion quantum chip confirm that the logical error rate falls below the physical error rate of this device, indicating that encoding already offers a practical benefit. These findings highlight IV as a viable design element for logical state preparation, especially as a design feature within circuit synthesis or reinforcement learning methods that aim to minimise depth under hardware constraints.