Program Synthesis for Programmable Data Planes

Generating P4 code by input-output examples

Master thesis (2023)

Authors

T. Jugariu Electrical Engineering, Mathematics and Computer Science

Contributors

F.A. Kuipers Networked Systems - EEMCS (supervisor 1)
C. Ji Networked Systems - EEMCS (supervisor 1)
S. Dumančić Algorithmics - EEMCS (supervisor 1)
Faculty
Electrical Engineering, Mathematics and Computer Science
Copyright: © 2023 Timo Jugariu
Program Synthesis P4 Programmable Data Planes Software Defined Networking
More Info
expand_more

Published Date

22-08-2023

Language

English

Reuse Rights

Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.

Faculty

Electrical Engineering, Mathematics and Computer Science

Abstract

An all-important step in the ambitious pursuit towards autonomous networks has been the introduction of Software Defined Networking which has advocated the concept of separating a network’s control plane from the data plane and creating a programmable controller with a wider view of the network. This innovation proved to be very promising, but the non-programmable data plane quickly became a limitation. 
The next step was brought by the emergence of the programmable switch architecture and P4, a language specifically designed for defining the behaviour of programmable network devices. P4 is a remarkably powerful language that allows the software developer to define almost any packet-processing functionality, all while abstracting away from the specifics of the target’s hardware architecture.
Despite its many benefits, P4 brings with it an additional layer of complexity for the network administrators, which may find themselves overwhelmed by having to learn a new programming language.
This report tackles this issue by presenting a prototype that is capable of synthesizing small P4 programs from pairs of input & output packets. Under the hood, the proposed solution uses a bottom-up enumerative synthesizer called Probe. This synthesizer was re-implemented, improved, and tailored to leverage the particularities of the problem domain.