Chopping in Continuous-Time Sigma-Delta Modulators

Conference paper (2017)

Authors

H. Jiang Electronic Instrumentation - EEMCS
B. Gonen Electronic Instrumentation - EEMCS
K.A.A. Makinwa Microelectronics
S. Nihtianova Electronic Instrumentation - EEMCS
Research Group
Electronic Instrumentation (EEMCS) (TU Delft)
1/f noise Continuous time Sigma delta Chopping Chopping artifacts Precision ADC Offset
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Published Date

2017

Language

English

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronic Instrumentation

Abstract

This paper discusses the use of chopping in continuous-time sigma-delta modulators where 1/f noise and offset need to be suppressed by continuous-time methods. An intuitive analysis of the artifacts related to chopping is presented. Aliasing of quantization noise is found to be the main problem, especially for chopping frequencies lower than the modulator's sampling frequency (fs). Correctly timed return-to-zero and switched-capacitor DACs are proposed as a solution to the aliasing problem. In both cases, the key idea is to synchronize DAC transitions with moments when the quantization noise at the input of the first integrator is low. Circuit level simulations are presented to validate the proposed techniques.

Files

08050951.pdf
(.pdf | 0.625 Mb)