Analysis and Design of an Integer-N Dual-slope SPLL with Gm-boosting

Abstract

This thesis presents a 10.4 GHz, sub-50 fs sampling PLL (SPLL) architecture with a dual-slope reference buffer, combined with Gm-boosting and current offset cancellation. To solve the problem of reduced lock-in range in ultra-low jitter sampling PLLs, previous state-of-the-art methods are analyzed, and a new theoretical lock-in range equation is derived for SPLLs that also takes the linear slope region into consideration, resulting in higher accuracy compared to previous works. Building on this theory, a new gm-boosting architecture is developed that removes the limit cycle limitation of previous gm-boosting architectures, resulting in higher Gm-boosting ratios. The PLL is designed in 40nm CMOS process and achieves a 48 fs RMS jitter and a lock-in range of 330 MHz while consuming 12.1 mW of power.