Fabrication of Nanoslits with <111> Etching TSWE Method

Conference Paper (2021)
Author(s)

H. Hong (Tsinghua University, TU Delft - Electronic Components, Technology and Materials)

Li Ye (Tsinghua University)

Ke Li (Beijing Jiaotong University)

PM Sarro (TU Delft - Electronic Components, Technology and Materials)

Guo Qi Zhang (TU Delft - Electronic Components, Technology and Materials)

Zewen Liu (Tsinghua University)

Research Group
Electronic Components, Technology and Materials
Copyright
© 2021 H. Hong, Li Ye, Ke Li, Pasqualina M Sarro, Kouchi Zhang, Zewen Liu
DOI related publication
https://doi.org/10.1109/NEMS51815.2021.9451489
More Info
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Publication Year
2021
Language
English
Copyright
© 2021 H. Hong, Li Ye, Ke Li, Pasqualina M Sarro, Kouchi Zhang, Zewen Liu
Research Group
Electronic Components, Technology and Materials
Pages (from-to)
174-177
ISBN (print)
978-1-6654-3008-1
ISBN (electronic)
978-1-6654-1941-3
Reuse Rights

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Abstract

In this paper, we report a modified three step anisotropic wet etching (TSWE) method to fabricate solid-state silicon nanoslits. The slit-opening process is performed by <111> crystal plane etching. The etching rate of the <111> crystal plane is reasonably slow as it is only 1/45 of the <100> etching rate, thus allowing and therefore good slits-opening controllability. By slowly etching the <111> crystal plane, the over-etching was effectively reduced. Perfectly rectangular nanoslits with different dimensions were successfully obtained. The smallest achieved feature size of the nanoslit is 8.3 nm.

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