Fabrication of Nanoslits with <111> Etching TSWE Method
Hao Hong (Tsinghua University, TU Delft - Electronic Components, Technology and Materials)
Li Ye (Tsinghua University)
Ke Li (Beijing Jiaotong University)
Pasqualina M. Sarro (TU Delft - Electronic Components, Technology and Materials)
Guoqi Zhang (TU Delft - Electronic Components, Technology and Materials)
Zewen Liu (Tsinghua University)
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Abstract
In this paper, we report a modified three step anisotropic wet etching (TSWE) method to fabricate solid-state silicon nanoslits. The slit-opening process is performed by <111> crystal plane etching. The etching rate of the <111> crystal plane is reasonably slow as it is only 1/45 of the <100> etching rate, thus allowing and therefore good slits-opening controllability. By slowly etching the <111> crystal plane, the over-etching was effectively reduced. Perfectly rectangular nanoslits with different dimensions were successfully obtained. The smallest achieved feature size of the nanoslit is 8.3 nm.