Fabrication of Nanoslits with <111> Etching TSWE Method

Conference paper (2021)

Authors

H. Hong Tsinghua University, Electronic Components, Technology and Materials - EEMCS
Li Ye Tsinghua University
Ke Li Beijing Jiaotong University
Pasqualina M Sarro Electronic Components, Technology and Materials - EEMCS
Kouchi Zhang Electronic Components, Technology and Materials - EEMCS
Zewen Liu Tsinghua University
Research Group
Electronic Components, Technology and Materials (EEMCS) (TU Delft)
Copyright: © 2021 H. Hong, Li Ye, Ke Li, Pasqualina M Sarro, Kouchi Zhang, Zewen Liu
DOI
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https://doi.org/10.1109/NEMS51815.2021.9451489
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Published Date

2021

Language

English

Reuse Rights

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Microelectronics

Research Group

Electronic Components, Technology and Materials

Abstract

In this paper, we report a modified three step anisotropic wet etching (TSWE) method to fabricate solid-state silicon nanoslits. The slit-opening process is performed by <111> crystal plane etching. The etching rate of the <111> crystal plane is reasonably slow as it is only 1/45 of the <100> etching rate, thus allowing and therefore good slits-opening controllability. By slowly etching the <111> crystal plane, the over-etching was effectively reduced. Perfectly rectangular nanoslits with different dimensions were successfully obtained. The smallest achieved feature size of the nanoslit is 8.3 nm.

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