Subthreshold Mismatch in Nanometer CMOS at Cryogenic Temperatures
P. A. T Hart (Student TU Delft)
M. Babaie (TU Delft - Electronics)
E. Charbon (Intel Corporation, École Polytechnique Fédérale de Lausanne)
A. Vladimirescu (University of California, TU Delft - OLD QCD/Charbon Lab, ISEP)
F. Sebastiano (TU Delft - (OLD)Applied Quantum Architectures)
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Abstract
Cryogenic device models are essential for the reliable design of the cryo-CMOS interface that enables large-scale quantum computers. In this paper, mismatch characterization and modeling of a 40-nm bulk CMOS process over the 4.2-300 K temperature range is studied, towards an all-operating-region mismatch model. An overall increase of variability is shown, in particular in the subthreshold region at cryogenic temperatures due to a dramatic increase of the subthreshold slope mismatch. Mismatch in strong inversion is modeled by the Croon model while the weak-inversion region is modeled by taking subthresh-old slope variability into account. This results in the first model capable of predicting mismatch over the whole range of operating regions and temperatures.