Software-Based Mitigation for Memory Address Decoder Aging

Conference paper (2019)

Authors

D.H.P. Kraak Computer Engineering - EEMCS
C.C. Gürsoy Tallinn University of Technology
I.O. Agbo Computer Engineering - EEMCS
M. Taouil Computer Engineering - EEMCS
Maksim Jenihhin Tallinn University of Technology
Jaan Raik Tallinn University of Technology
S. Hamdioui Quantum & Computer Engineering
Research Group
Computer Engineering (EEMCS) (TU Delft)
Copyright: © 2019 D.H.P. Kraak, C.C. Gürsoy, I.O. Agbo, M. Taouil, M. Jenihhin, J. Raik, S. Hamdioui
DOI
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https://doi.org/10.1109/LATW.2019.8704595
Mitigation Aging Memory Address decoder
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Published Date

2019

Language

English

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Faculty

Electrical Engineering, Mathematics and Computer Science

Department

Quantum & Computer Engineering

Research Group

Computer Engineering

Abstract

Integrated circuits typically contain design margins to compensate for aging. As aging impact increases with technology scaling, bigger margins are necessary to achieve the desired reliability. However, these increased margins lead to a reduced performance and lower yield. Alternatively, mitigation schemes can be deployed to reduce the aging. This paper proposes a software-based method to mitigate the aging of the memory's address decoder logic due to Bias Temperature Instability. The method is based on periodically applying a rejuvenation application on top of a user application. The goal of the rejuvenation application is to recover aged transistors of the critical paths of the address decoder. The experimental results show that the proposed method significantly reduces aging in cases when applications consist of memory access patterns that result in an unbalanced stress in the address decoder logic. In particular, it reduces the degradation of the address decoder's setup delay by up to 43% with an execution overhead of only 1%.