A Low-Jitter Sampling PLL with ADC-based Reference Sampling for Extended Capture Range

Abstract

Phase-locked loops (PLLs) are essential building blocks in communication, sensing, and high-speed clock-generation systems. This thesis presents a wideband sampling PLL architecture that combines an ADC-based reference-sampling digital PLL (ADC-RSDPLL) for robust frequency acquisition with a sampling PLL (SPLL) for low-jitter clock generation. The ADC-based auxiliary loop avoids the stringent resolution, dynamic-range, and linearity requirements associated with conventional time-to-digital-converter- and counter-based acquisition loops. A 4-bit flash ADC-based phase detector together with in-phase and quadrature (IQ) sampling is employed to extend the effective phase capture range. An automatic lock-detection state machine sequences the loop through PVT calibration, acquisition, and tracking modes, enabling a controlled handover from the digital acquisition loop to the sampling PLL.

The PLL, designed in 28nm CMOS technology, operates from a 100~MHz reference and covers a 12--20~GHz output-frequency range. The implementation includes a 12--20~GHz LC-VCO. Post-layout simulations were performed on the design to demonstrate the effectiveness of the proposed architecture in providing robust wide-range frequency acquisition while preserving the low-jitter benefit of a sampling PLL during steady-state operation. The designed PLL also performs well among the state-of-the-art designs.