Mapping of Lattice Surgery-based Quantum Circuits on Surface Code Architectures
L. Lao (TU Delft - QuTech Advanced Research Centre, TU Delft - Computer Engineering)
B. van Wee (Student TU Delft)
I. Ashraf (TU Delft - FTQC/Bertels Lab, TU Delft - QuTech Advanced Research Centre)
J. van Someren (TU Delft - QuTech Advanced Research Centre, TU Delft - Computer Engineering)
Nader Khammassi (TU Delft - FTQC/Bertels Lab, TU Delft - QuTech Advanced Research Centre)
K Bertels (TU Delft - (OLD)Quantum Computer Architectures, TU Delft - QuTech Advanced Research Centre)
Carmen Garcia García Almudever (TU Delft - Computer Engineering, TU Delft - QuTech Advanced Research Centre)
More Info
expand_more
Other than for strictly personal use, it is not permitted to download, forward or distribute the text or part of it, without the consent of the author(s) and/or copyright holder(s), unless the work is under an open content license such as Creative Commons.
Abstract
Quantum error correction (QEC) and fault-tolerant (FT) mechanisms are essential for reliable quantum computing. However, QEC considerably increases the computation size up to four orders of magnitude. Moreover, FT implementation has specific requirements on qubit layouts, causing both resource and time overhead. Reducing spatial-temporal costs becomes critical since it is beneficial to decrease the failure rate of quantum computation. To this purpose, scalable qubit plane architectures and efficient mapping passes including placement and routing of qubits as well as scheduling of operations are needed. This paper proposes a full mapping process to execute lattice surgery-based quantum circuits on two surface code architectures, namely a checkerboard and a tile-based one. We show that the checkerboard architecture is 2x qubit-efficient but the tile-based one requires lower communication overhead in terms of both operation overhead (up to 86%) and latency overhead (up to 79%).