A Dynamically Reconfigurable RISC-V Processor Based on the MOLEN Paradigm
D.M. van den Berg (TU Delft - Electrical Engineering, Mathematics and Computer Science)
Stephan Wong – Mentor (TU Delft - Computer Engineering)
Rene Van Leuken – Graduation committee member (TU Delft - Signal Processing Systems)
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Abstract
In this thesis, we present a RISC-V processor that is extended with the MOLEN ISA extension, thereby granting it dynamic reconfiguration capabilities. The reconfigurable microcode (ρμ-code) of the MOLEN paradigm is modified to be suitable for (FPGA) implementation in the 64-bit Linux-capable CVA6 RISC-V processor. The set instruction performs reconfigurations by pointing it to a partial bitstream address, after which the execute instruction can perform operations on the reconfigured hardware. To this end, the concept of nested ρμ-code is presented, in which the reconfigurable opcodes are encapsulated in regular RISC-V instructions. Furthermore, a status instruction is introduced to enable the reconfiguration to be performed in the background. Consequently, the reconfiguration latency can be hidden, by allowing the CPU to do useful work during the reconfiguration. Using various experiments, it is demonstrated that the proposed implementation has a near-optimal reconfiguration performance and that the reconfiguration latency can be effectively hidden in typical cases.