Bridging the Speed-Accuracy Gap

Abstract

Power side-channel attacks pose a serious threat to cryptographic hardware implementations. To avoid deploying insecure implementations, it is essential to perform side-channel leakage assessments at the pre-silicon stage. Register Transfer Level (RTL)-level or gate-level power traces-generated, for example using SpyGlass, can be produced very efficiently but suffer from limited accuracy. In contrast, post-layout simulations provide a much higher accuracy but are prohibitively time-consuming. In this work, we propose a hybrid approach that extracts layout information, including timing and parasitic effects, and augments the gate-level netlist with this data. This approach enables fast pre-silicon power trace generation that accurately embeds post-layout parasitics. Our results show that power traces generated from gate-level and transistor-level simulations, both augmented with layout information, perform similarly in key-ranking anlysis and have a low Euclidean distance, while the gate-level simulations are 19 x-125 x faster to generate.