A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology

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A 200Gb/s PAM-4 Transmitter with Hybrid Sub-Sampling PLL in 28nm CMOS Technology

Conference Paper (2022)

Author(s)

Zhongkai Wang (University of California)

Minsoo Choi (Samsung Semiconductor)

Paul Kwon (University of California)

Kyoungtae Lee (University of California)

Bozhi Yin (University of California)

Zhaokai Liu (University of California)

Kwanseo Park (University of California)

Ayan Biswas (University of California)

Sijun Du (TU Delft - Electronic Instrumentation)

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Transmitter CMOS SerDes 28nm Sub-sampling PLL

DOI related publication

https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830237 Final published version

To reference this document use

https://resolver.tudelft.nl/uuid:e438cca0-245c-4bb0-8f5b-4055b186752b

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Publication Year

2022

Language

English

Bibliographical Note

Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Pages (from-to)

34-35

ISBN (electronic)

978-1-6654-9772-5

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460

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Abstract

This paper presents a complete 200Gb/s PAM-4 transmitter (TX) in 28nm CMOS technology. The transmitter features a hybrid sub-sampling PLL (SSPLL) with a delta-sigma (?S) modulator, clock distribution network with flexible timing control, and data path with a hybrid 5-tap Feed-Forward Equalizer (FFE) and T-coil for bandwidth extension. The prototype chip achieves 4.69 pJ/bit efficiency, 54mV eye height, 0.27UI eye width, and 97% RLM under -6dB channel loss at 50GHz.

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