A Workload-Aware Design Space Exploration of Analog Computation in Memory Architectures
R. Cavalini (TU Delft - Electrical Engineering, Mathematics and Computer Science)
J.S.S.M. Wong – Graduation committee member (TU Delft - Electrical Engineering, Mathematics and Computer Science)
B. Abdikivanani – Graduation committee member (TU Delft - Electrical Engineering, Mathematics and Computer Science)
K. Stavrakakis – Mentor (TU Delft - Electrical Engineering, Mathematics and Computer Science)
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Abstract
Computation in Memory (CIM) replaces the traditional von Neumann architecture by integrating processing units within memory. This integration reduces energy consumption and latency associated with frequent data transfers between memory and processing units. A frequent application of CIM accelerators is in workloads dominated by Vector-Matrix Multiplication (VMM).
This thesis presents a workload-aware design space exploration (DSE) modelling framework for analog CIM architectures. The modelling utilises a Python wrapper for an analog CIM simulator (ACIMSIM) to evaluate Convolutional Neural Networks (CNN), Multilayer Perceptron (MLP), Fast Fourier Transform (FFT), and Compressed Sensing (CS) workloads on a 32 nm technology node. Workloads are assessed in terms of energy, latency, area, and accuracy, considering factors such as parallel and sparse differential mapping, input and weight sizes, memory cell size, crossbar array dimensions, ADC precision, ADC sharing factor, and maximum activated rows.
The results indicate that no single CIM architecture achieves optimal performance across all workloads and metrics. ADC sharing significantly influences latency and area, whereas energy and accuracy are more dependent on workload characteristics, mapping style, and numerical precision. Sparse differential mapping typically improves area efficiency, while parallel differential mapping is preferable for latency-efficient designs. These findings suggest that CIM architectures should be optimised to meet workload-specific requirements rather than relying on a fixed, general-purpose design.
Future experiments can build on this modelling framework by improving the execution speed of the ACIMSIM backend, adding more configurations and mapping styles, implementing accuracy calculations for memory cell sizes greater than 1, and extending the framework to include system-level components.