RC
R. Cavalini
info
Please Note
<p>This page displays the records of the person named above and is not linked to a unique person identifier. This record may need to be merged to a profile.</p>
2 records found
1
Computation in Memory (CIM) replaces the traditional von Neumann architecture by integrating processing units within memory. This integration reduces energy consumption and latency associated with frequent data transfers between memory and processing units. A frequent application of CIM accelerators is in workloads dominated by Vector-Matrix Multiplication (VMM).
This thesis presents a workload-aware design space exploration (DSE) modelling framework for analog CIM architectures. The modelling utilises a Python wrapper for an analog CIM simulator (ACIMSIM) to evaluate Convolutional Neural Networks (CNN), Multilayer Perceptron (MLP), Fast Fourier Transform (FFT), and Compressed Sensing (CS) workloads on a 32 nm technology node. Workloads are assessed in terms of energy, latency, area, and accuracy, considering factors such as parallel and sparse differential mapping, input and weight sizes, memory cell size, crossbar array dimensions, ADC precision, ADC sharing factor, and maximum activated rows.
The results indicate that no single CIM architecture achieves optimal performance across all workloads and metrics. ADC sharing significantly influences latency and area, whereas energy and accuracy are more dependent on workload characteristics, mapping style, and numerical precision. Sparse differential mapping typically improves area efficiency, while parallel differential mapping is preferable for latency-efficient designs. These findings suggest that CIM architectures should be optimised to meet workload-specific requirements rather than relying on a fixed, general-purpose design.
Future experiments can build on this modelling framework by improving the execution speed of the ACIMSIM backend, adding more configurations and mapping styles, implementing accuracy calculations for memory cell sizes greater than 1, and extending the framework to include system-level components.
...
This thesis presents a workload-aware design space exploration (DSE) modelling framework for analog CIM architectures. The modelling utilises a Python wrapper for an analog CIM simulator (ACIMSIM) to evaluate Convolutional Neural Networks (CNN), Multilayer Perceptron (MLP), Fast Fourier Transform (FFT), and Compressed Sensing (CS) workloads on a 32 nm technology node. Workloads are assessed in terms of energy, latency, area, and accuracy, considering factors such as parallel and sparse differential mapping, input and weight sizes, memory cell size, crossbar array dimensions, ADC precision, ADC sharing factor, and maximum activated rows.
The results indicate that no single CIM architecture achieves optimal performance across all workloads and metrics. ADC sharing significantly influences latency and area, whereas energy and accuracy are more dependent on workload characteristics, mapping style, and numerical precision. Sparse differential mapping typically improves area efficiency, while parallel differential mapping is preferable for latency-efficient designs. These findings suggest that CIM architectures should be optimised to meet workload-specific requirements rather than relying on a fixed, general-purpose design.
Future experiments can build on this modelling framework by improving the execution speed of the ACIMSIM backend, adding more configurations and mapping styles, implementing accuracy calculations for memory cell sizes greater than 1, and extending the framework to include system-level components.
...
Computation in Memory (CIM) replaces the traditional von Neumann architecture by integrating processing units within memory. This integration reduces energy consumption and latency associated with frequent data transfers between memory and processing units. A frequent application of CIM accelerators is in workloads dominated by Vector-Matrix Multiplication (VMM).
This thesis presents a workload-aware design space exploration (DSE) modelling framework for analog CIM architectures. The modelling utilises a Python wrapper for an analog CIM simulator (ACIMSIM) to evaluate Convolutional Neural Networks (CNN), Multilayer Perceptron (MLP), Fast Fourier Transform (FFT), and Compressed Sensing (CS) workloads on a 32 nm technology node. Workloads are assessed in terms of energy, latency, area, and accuracy, considering factors such as parallel and sparse differential mapping, input and weight sizes, memory cell size, crossbar array dimensions, ADC precision, ADC sharing factor, and maximum activated rows.
The results indicate that no single CIM architecture achieves optimal performance across all workloads and metrics. ADC sharing significantly influences latency and area, whereas energy and accuracy are more dependent on workload characteristics, mapping style, and numerical precision. Sparse differential mapping typically improves area efficiency, while parallel differential mapping is preferable for latency-efficient designs. These findings suggest that CIM architectures should be optimised to meet workload-specific requirements rather than relying on a fixed, general-purpose design.
Future experiments can build on this modelling framework by improving the execution speed of the ACIMSIM backend, adding more configurations and mapping styles, implementing accuracy calculations for memory cell sizes greater than 1, and extending the framework to include system-level components.
This thesis presents a workload-aware design space exploration (DSE) modelling framework for analog CIM architectures. The modelling utilises a Python wrapper for an analog CIM simulator (ACIMSIM) to evaluate Convolutional Neural Networks (CNN), Multilayer Perceptron (MLP), Fast Fourier Transform (FFT), and Compressed Sensing (CS) workloads on a 32 nm technology node. Workloads are assessed in terms of energy, latency, area, and accuracy, considering factors such as parallel and sparse differential mapping, input and weight sizes, memory cell size, crossbar array dimensions, ADC precision, ADC sharing factor, and maximum activated rows.
The results indicate that no single CIM architecture achieves optimal performance across all workloads and metrics. ADC sharing significantly influences latency and area, whereas energy and accuracy are more dependent on workload characteristics, mapping style, and numerical precision. Sparse differential mapping typically improves area efficiency, while parallel differential mapping is preferable for latency-efficient designs. These findings suggest that CIM architectures should be optimised to meet workload-specific requirements rather than relying on a fixed, general-purpose design.
Future experiments can build on this modelling framework by improving the execution speed of the ACIMSIM backend, adding more configurations and mapping styles, implementing accuracy calculations for memory cell sizes greater than 1, and extending the framework to include system-level components.
Bachelor thesis
(2022)
-
R. Cavalini, I. Hassan, T. Pouwels, B. Abdikivanani, A.J. van der Veen, R.M.A. van Puffelen, P.M. Sarro
This report entails one of two subsystems in a joint project to provide a web-based platform for smartwatch data acquisition, for applications in healthcare. In this work, we design and implement algorithms for human activity recognition using various machine learning approaches and test them on data acquired online as well as using our own developed platform. Together with the web-based platform, this provides a solid base for more research using data gathered from smartwatches. The human activity recognition is implemented first using a classical machine learning approach
with feature extraction and a random forest classifier. Next, both convolutional neural network and a recurrent neural network are implemented using Tensorflow [1]. We further perform several tests to investigate: (i) the optimal segment size with respect to classification accuracy, (ii) the effect of filtering and preprocessing on the classification results, and (iii) the best classifier for activity detection. ...
with feature extraction and a random forest classifier. Next, both convolutional neural network and a recurrent neural network are implemented using Tensorflow [1]. We further perform several tests to investigate: (i) the optimal segment size with respect to classification accuracy, (ii) the effect of filtering and preprocessing on the classification results, and (iii) the best classifier for activity detection. ...
This report entails one of two subsystems in a joint project to provide a web-based platform for smartwatch data acquisition, for applications in healthcare. In this work, we design and implement algorithms for human activity recognition using various machine learning approaches and test them on data acquired online as well as using our own developed platform. Together with the web-based platform, this provides a solid base for more research using data gathered from smartwatches. The human activity recognition is implemented first using a classical machine learning approach
with feature extraction and a random forest classifier. Next, both convolutional neural network and a recurrent neural network are implemented using Tensorflow [1]. We further perform several tests to investigate: (i) the optimal segment size with respect to classification accuracy, (ii) the effect of filtering and preprocessing on the classification results, and (iii) the best classifier for activity detection.
with feature extraction and a random forest classifier. Next, both convolutional neural network and a recurrent neural network are implemented using Tensorflow [1]. We further perform several tests to investigate: (i) the optimal segment size with respect to classification accuracy, (ii) the effect of filtering and preprocessing on the classification results, and (iii) the best classifier for activity detection.