SWEET-DREAM

Abstract

Computation-in-memory (CIM) accelerators offer energy and area efficiency gains but remain vulnerable to power side-channel leakage. This paper presents a comprehensive security analysis of a pipelined digital SRAM-based CIM accelerator named DREAM-CIM. We first identify leakage mechanisms through pre-silicon modeling and gate-level simulation, and then confirm their presence on a 22 nm post-silicon prototype. Moreover, to mitigate leakage, we introduce a Globally Synchronous and Locally Asynchronous (GSLA) countermeasure approach that desynchronizes immediate-pipeline-update registers and randomizes local activity while preserving functional correctness. Security is evaluated using post-silicon power traces under standard side-channel analyses, demonstrating effective leakage suppression. The countermeasure incurs ≈ 53% area and ≈ 74% energy overhead relative to the baseline design. Compared to masking-based countermeasures, GSLA achieves a reduction of ≈ 8.9 × and ≈ 9.2 × in area and energy overhead, respectively.